A. Field of the Invention
The present invention relates to MOS semiconductor devices used in switching power supplies. Specifically, the invention relates to trench gate semiconductor devices and the method of manufacturing the trench gate semiconductor devices. More specifically, the invention relates to a trench gate MOSFET including a source region and a contact-trench formed by self-alignment or a trench gate IGBT including a source region and a contact-trench formed by self-alignment. More specifically, the invention relates also to the method of manufacturing the trench gate MOSFET or the trench gate IGBT.
B. Description of the Related Art
Generally, it is required for the semiconductor devices used in switching power supplies to sustain the voltage applied thereto in the OFF-state and to exhibit low resistance (low ON-state resistance) against the current made to flow in the ON-state of the semiconductor devices. In the low-voltage semiconductor devices, capable of sustaining a voltage as high as several tens V (the breakdown voltage thereof is several tens V), the channel resistance in the MOS structure occupies a large part of the ON-state resistance. To reduce the channel resistance per unit area, the semiconductor devices (trench gate MOSFET's and trench gate IGBT's) having a trench gate structure that facilitates increasing the channel density mainly have been used. For further increasing the channel density, the spacing between the trenches (trench gates), in which a gate is formed, has been made to be narrower and narrower.
Now the standard layer structure in a trench gate MOSFET will be described. The trench gate MOSFET includes an n-type substrate, the resistance of which is low; a drain layer on the back surface of the substrate; an n-type drift layer, the resistance of which is high, on the drain layer for sustaining the breakdown voltage; and a p-type body region on the front surface side of the drift layer. In the surface portion of the p-type body region, an n+ source region and a p+ body-contact region are formed selectively. A trench is formed from the surface portion of the p-type body region in contact with the n+ source region. The trench bottom plane is in contact with the n-type drift layer. A gate oxide film is formed on the trench inner wall. Polysilicon that works as a gate electrode is loaded in the trench with the gate oxide film interposed between the polysilicon and the trench inner wall.
An insulator such as a silicon oxide film is disposed on the gate electrode. A source electrode, in contact commonly with the n+ source region surface and the p+ body-contact region surface, covers the insulator. In forming a contact region, through which the source electrode is in contact with the n+ source region surface and the p+ body-contact region surface, it is necessary to form a mask pattern that covers the regions other than the n+ source region and the p+ body-contact region so as not to make the source electrode short-circuit to the gate electrode nor to the drain layer. In order for the source electrode not to short-circuit to the gate electrode or to the drain layer, it is necessary to design the trench gate MOSFET with a certain size margin for absorbing the alignment deviations of the mask pattern. A design that considers the size margin causes a barrier against increasing the pattern density, including the channel density.
To overcome the barrier described above, the following U.S. Pat. No. 6,818,946 and U.S. Pat. No. 6,351,009, and Bing-Yue Tsui et al., “A Novel Fully Self-Aligned Process for High Cell Density Trench Gate Power MOSFETs”, IEEE ISPSD 2004, Proceeding of 2004 International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, each describe the structure shown in FIG. 2(a), and the method for forming the structure shown in FIG. 2(a). As shown in FIG. 2(a), the upper layer of gate electrode (gate polysilicon) 100 used for the trench gate MOSFET is polished by etching such that the loaded gate polysilicon 100 surface is positioned lower than substrate surface 101. Using silicon oxide film 102 covering polished gate polysilicon 100 and substrate surface 101 for a mask, n+ source region 104 is formed in the upper side wall of trench 103 by oblique ion implantation into the side wall of trench 103. By employing a structure in which n+ source region 104 is formed in the upper side wall of trench 103, it is possible to omit a mask alignment. Since no mask displacement is caused, it is not necessary to consider any mask alignment deviation in the device design in advance. Therefore, it is possible to further increase the channel density.
U.S. Pat. No. 6,921,939 describes another trench gate MOSFET structure shown in FIG. 2(b), in which n+ source region 112 is formed by a self-alignment technique that does not employ any mask and the body resistance of a parasitic bipolar junction transistor (hereinafter referred to as a “parasitic BJT”) is designed to be low.
According to the method for manufacturing the trench gate MOSFET structure shown in FIG. 2(b), the upper portion of trench 113, in the lower portion of which polysilicon gate 114 is formed, is filled with insulator 115. Then, the entire silicon surface, in which n+ source region 112 is formed, is etched a little such that the silicon surface is positioned lower than the insulator 115 upper surface. A spacer is formed utilizing the step formed as described above between insulator 115 and the silicon. Then, the silicon is etched using the spacer as a mask for forming body-contact-trench 116 for reducing the body resistance of the parasitic BJT. By employing the method as described above, n+ source region 112 and body-contact-trench 116 are formed securely without using any mask. Thus, a high channel density and low body resistance are obtained simultaneously.
Japanese Unexamined Patent Application Publication No. 2006-157016 describes another manufacturing method. Trenches spaced apart from each other by a mesa region are formed in a semiconductor substrate. A polysilicon gate electrode is formed in the trench with a gate insulator film interposed between the gate electrode and the trench. A concave portion is formed in the upper portion of the gate electrode. An insulator film is formed on the substrate surface. By a flattening treatment, the concave portion in the upper portion of the gate electrode positioned lower than the substrate surface is filled with the insulator film and the substrate surface is exposed. Using the insulator films filling the concave portions on the gate electrodes as masks, the portions of the substrate between the trenches are etched such that contact holes are formed in the substrate surface between the trenches.
In the trench gate MOSFET structure described in U.S. Pat. No. 6,818,946 and U.S. Pat. No. 6,351,009, the body region between the n+ source regions becomes narrower as the spacing between the trenches is made to be narrower. This implies that the body resistance of the parasitic BJT formed of the n+ source region, the body region and the drift region becomes higher. Since the parasitic BJT is liable to be turned off, when an avalanche breakdown is caused between the drift region and the n+ source region, the avalanche withstanding capability is liable to be low.
To minimize the n+ source region width in the trench gate MOSFET structure described in U.S. Pat. No. 6,921,939, it is necessary to minimize the spacer width, since the spacer width depends on the etching amount of the silicon surface. Since it is necessary to minimize the etching amount, it is difficult to control the manufacturing process. Since the heavily doped surface portion of n+ source region is polished by etching, the impurity concentration in the remaining n+ source region surface becomes low. Therefore, the contact resistance between the n+ source region surface and the source electrode is liable to be high.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a trench gate semiconductor device that facilitates increasing the channel density thereof and reducing the body resistance of the parasitic BJT therein. It would be further desirable to provide a method of manufacturing a trench gate semiconductor device that facilitates increasing the channel density thereof and reducing the body resistance of the parasitic BJT therein.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.